35
2552K–AVR–04/11
ATmega329/3290/649/6490
9.
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed, see “SMCR – Sleep Mode Control Register” on page 39.
The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise
Reduction, Power-down, Power-save, or Standby) will be activated by the SLEEP instruction.
See Table 9-1 on page 35 for a summary. If an enabled interrupt occurs while the MCU is in a
sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-
up time, executes the interrupt routine, and resumes execution from the instruction following
SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up
from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the
Reset Vector.
Figure 8-1 on page 26 presents the different clock systems in the ATmega329/3290/649/6490,
and their distribution. The figure is helpful in selecting an appropriate sleep mode.
Notes:
1. Only recommended with external crystal or resonator selected as clock source.
2. If either LCD controller or Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt
Table 9-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
Sleep
Mode
cl
k
CP
U
cl
k
FLA
SH
cl
k
IO
cl
k
AD
C
cl
k
AS
Y
Main
Cloc
k
Sour
ce
Enab
led
Timer
Os
c
Enab
led
INT0
an
d
P
in
Chang
e
USI
Sta
rt
Cond
iti
o
n
LCD
Cont
ro
ller
Timer2
SPM/EE
P
R
O
M
Re
ad
y
AD
C
Oth
e
rI/O
Idle
X
XX
X
ADC
Noise
Reduction
X
XX(2)
XX
Power-
down
X
Power-
save
X
XX
X
Standby(1)
XX(3)
X
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